1. Technical Field
This invention generally relates to electronic circuits, and more specifically relates to a method for electronic circuit design.
2. Background Art
Integrated circuits (ICs) are semiconductor devices consisting of many components arranged on a base called a wafer. Semiconductors are formed from material that allows current to flow under certain circumstances, making them indispensable in all sorts of environments from computers to cellular phones to calculators and beyond. ASICs are integrated circuits that are designed to perform a specific function for a specific customer, such as a chip that controls a talking toy or a chip for use in a communications satellite. Frequently an ASIC will share some features with other ASICs previously produced. This partial duplication leads to the creation of standard cell libraries made up of components that perform certain logical functions. These componentsxe2x80x94the cellsxe2x80x94themselves consist of more basic units called devices. When an ASIC""s design calls for a certain function to be performed, a cell that accomplishes that function can be selected from the cell library instead of being designed from the ground up. This time-saving step becomes very important when it is considered that large ASIC manufacturers may produce several hundred ASICs in a year.
The design phase of an ASIC includes the performance of various tests to ensure the chip meets critical performance criteria, including the two fundamental concerns in chip design: timing and noise, which are defined in the next two paragraphs. If these or any other chip requirements are not met the chip must be redesigned and retested until they are. The redesign of a circuit involves such steps as altering the physical layout of chip cells, replacing certain cells with new cells, and changing chip parameters like power level or cell size.
The current trend in semiconductor design is toward lower operating power. Lower power means lower voltages supplied to the semiconductor, and lower voltages at which the semiconductor switches. This latter voltage for a cell is called the switching threshold for the cell. This switching threshold for the cell is the value of the input signal such that an input less than this value will be recognized by the cell as a xe2x80x9czero,xe2x80x9d and an input greater than this value will be recognized as a xe2x80x9cone.xe2x80x9d Because cells work by being switched on or off in response to precise voltage signals, it is important that those signals are not the result of unwanted noise in the circuit. In this context, xe2x80x9cnoisexe2x80x9d refers to an unwanted electromagnetic disturbance that reduces the clarity of a signal. Here, the signal is an input voltage sufficiently far above or below the cell threshold as to be unambiguously recognized as either a xe2x80x9czeroxe2x80x9d or a xe2x80x9conexe2x80x9d telling the cell to turn on or turn off. The disturbance is any such unwanted signal that exceeds the cell threshold and causes the cell to switch falsely. As operating power, and thus power grid supply voltage Vdd and cell switching threshold voltages decrease, noise spike voltages become a greater percentage of the switching threshold and become increasingly problematic, causing an increasing number of false switches.
More common than the false switching problem is the problem of switching delay. This is the timing problem mentioned above. Recall that the semiconductors which are the building blocks of all integrated circuits are materials that sometimes allow and sometimes prevent the flow of current. The opposite states of current flow and current cessation are sometimes referred to as xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d or as xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d respectively. Timing errors can occur when adjacent wires undergo transitions that interfere with each other. For example, when one wire, the victim, is attempting a transition from on to off, an adjacent wire, the aggressor, might be transitioning from off to on. While the aggressor""s effect might be insufficient to cause a false switch (a voltage rise corresponding to the on position) in the victim, it can sometimes be enough to delay or even reverse for a moment the desired transition in the victim, thus preventing a smooth switch and lengthening the time needed for it. This is one way in which noise problems lead to timing problems.
One approach to fixing the noise/timing problem is to adjust various parameters of the system such as spacing, power, and cell size. Spacing adjustments, for example, are effective because they change the coupling capacitance between adjacent conductors. In other words, because noise can be coupled from one conductor to another by their mutual capacitance, increasing the separation between these wires reduces coupling capacitance and therefore reduces the amount of noise injected.
The effects of such changes or adjustments, whether to spacing, power, or some other parameter, can be predicted with reasonable accuracy; the difficulty lies in the fact that it is nearly impossible to predict exactly which change out of an uncountably large number of possible changes is necessary to fix a specific problem. Trial and error, therefore, becomes the only currently viable solution approach, but is itself severely flawed. Besides being inefficient and time consuming, it is ill-equipped to discover problems early in the chip design process. Yet noise sensitivity problems are best discovered as early in the design process as possible in order to avoid the costs of redesign or reconstruction activity.
There also exist farther drawbacks to the solution approach being described. Each parameter adjustment, besides being impossible to select with confidence, poses potentially unwanted and harmful consequences to other parameters in the system. Every adjustment propagates through the system, potentially degrading performance. Trial and error, clearly, leaves much to be desired as an approach to chip-design improvement.
The prior art describes cell libraries-collections of cells useful in redesigning circuits using this trial and error process. The method of replacing an under-performing original cell with an alternate cell from a pre-built cell library is known. A major problem with this basic approach is that a substitution made to fix a problem with one parameter of the IC often creates one or more problems with other parameters. For example, an original cell underperforming with respect to noise tolerance might be replaced with a more noise-tolerant cell. But that replacement cell may create a new set of timing problems that make it just as problematic as the original. A second replacement cell may have altered power requirements that worsen the problem further. Such introduced problems can propagate through the system, causing trouble spots all along the circuit path. Without a way to guarantee that a replacement cell fixes the problem it is intended to solve without causing new problems in the process, such trial and error substitution could potentially fall into an infinite loop where every attempted fix leads to further problems in IC performance. That is a worst-case and perhaps unlikely scenario but it would not be at all uncommon for trial and error problem solving to take at least several hours. With the demand for ASICs growing steadily, time saving techniquesxe2x80x94especially in the timexe2x80x94intensive design phase-are becoming increasingly more important. Therefore, there exists a need to provide an efficient way to address and fix ASIC design problems in a manner that avoids the creation of new problems that can propagate through the system.
According to the present invention, a cell library is provided, each cell having known values of one parameter but having differing values of another parameter. The library cells are ordered in such a way that successive cells in the order exhibit an orderly incrementation of the parameter being changed. Said another way, the cells are ordered from one extreme to the other extreme value of featured parameter F. In one embodiment of the invention the changing parameter can be noise tolerance and the known parameter can be timing. Other cell parameters including size, power requirements, and current capacity could also be either the changing or the known parameter. This means that a substitution of any cell from the library for any other library cell, or the original cell, will have a negligible effect on, to take the original example, the chip""s timing characteristics because that is the parameter held substantially constant or allowed to vary in a known and acceptable way. A chip designer can thus vary the noise tolerances of the IC as needed, confident that such modifications will not create timing problems in the circuit.
It will be understood that the idea of constructing a library with increasing noise rejection, no timing impact, and no size change is of limited use. It can generally be applied to multi-stage cells with limited opportunity for improvement of noise rejection. A more useful approach would be a library with increasing noise rejection and known timing change. Thus, although for simplicity the invention may at times herein be described in terms of a constant or substantially constant parameter, it will be apparent to those skilled in the art that the invention achieves broader utility when the parameter is not necessarily constant, but simply has known and acceptable variation.
One embodiment of the present invention thus involves the provision of a cell library containing IC design element cells sorted into groups of functionally-equivalent cells. Each of the cells in each group have a set of parameters, one of which is a parameter whose value is constant or allowed to vary in an acceptable way, and another of which is a changing parameter, all of which together comprise the total makeup of each cell. After an ASIC is designed its performance with respect to the changing parameter, called featured parameter F, is tested. If problems are found the underperforming cell is marked for replacement, the appropriate library group is accessed, and a replacement cell chosen. The replacement cell is the first unused cell in the library group. This process is repeated until the ASIC performance is satisfactory.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of certain embodiments of the invention, as illustrated in the accompanying drawings.